This invention relates generally to a system and method for interfacing systems within a computer system and in particular to a system and method for interfacing an input/output system to a host computer over a high speed computer bus.
Computer systems, and in particular, central processing units (CPUs) in the computer system require a certain amount of memory to store software application code, operating system code as well as data. During the operation of a typical computer system, the CPU executes the application code stored in the memory and stores and/or retrieves data from the memory. In addition to the memory, the CPU may also require additional hardware circuitry and memory to interface with different electrical computer buses which may have different purposes and different bus standards. These computer buses may connect input/output (I/O) systems and devices to the CPU, for example.
Some of these input/output devices may have a microprocessor or microcontroller located in the input/output device to process data being communicated to the input/output device to improve the speed or functionality of the I/O operations. Other devices may not, so the CPU in the computer system may have to process all of the input/output devices instructions and data as well as its own instructions and data. This can degrade the speed of the CPU. The performance of the input/output device is also slow because the instructions and data from the input/output device at times may have a lower priority than the CPU's own data and instructions. Some typical input/output devices may have some intelligence, such as a microcontroller or microprocessor so that instructions of the device can be executed, and data can be processed by the microprocessor located within the input/output device. Therefore, the speed of processing the instructions and data of the input/output device is not dependent on the speed of the CPU in the computer system. These input/output devices normally require a local memory for storing the software application code being executed by the microprocessor in the input/output device and the data operated on by the microprocessor. The additional memory in the input/output device increases its cost and increases its overall physical size requirements. It is often desirable that data transfers occur between the local memories for the input/output device and the main memory of the computer system.
Many system buses and memory devices are capable of high speed data transfers, such as block transfers, in which a block of sequential memory addresses is transferred. These high speed transfers are known as "burst" transfers since a sequential block of data may be rapidly transferred (e.g., bursted) to another memory location or another memory connected to the same computer bus. These burst transfers are very efficient for general bus operations (e.g., the transfer of commands and data from different units within a computer system), but cannot adequately serve a microprocessor executing software code because the software code is typically accessed from non-sequential memory locations within the memory and thus requires non-sequential accessing of the memory which is not compatible with the sequential memory address burst transfers over computer buses. The burst transfer of sequential memory addresses also does not adequately serve any other type of retrieval or processing of non-sequential data.
None of the known systems provides a general purpose, processor unspecific memory architecture which can take advantage of the high speed sequential data transfers possible with a computer bus while also serving as the main memory for a microprocessor in an input/output device which requires randomly accessible data. It is desirable to provide a memory architecture and system that can take advantage of high speed burst transfers over a high speed computer bus for input/output devices that require randomly accessible data.
Thus, there is a need for a system and method for improved, more efficient communication of data between an input/output device and a computer system over a high speed computer bus which avoids the foregoing and other problems of known systems and methods, and it is to this end that the present invention is directed.